Digital systems typically work on a synchronous clock edge. Thus, provided that propagation delays and set up time are properly determined, on the appropriate clock edge a determined signal state received at an input of a latching device will properly propagate to the output of the latching device.
Communication of a digital signal often must be accomplished between subsystems which do not share a common clock, and thus the received digital signal is essentially asynchronous to the receiving subsystem. In the event that the change in state of the received signal does not meet the setup and hold requirements of the receiving latching device prior to the clocking signal of the receiving latching device, the receiving latching device may present a metastable state, i.e. the output of the receiving latching device may oscillate for a predetermined amount of time until settling into a particular state. Furthermore, there is no guarantee that the ultimate particular state is reflective of the state of the received signal at the time of the clocking signal.
Synchronizers are known devices whose function is to capture an incoming signal, and synchronize changes in the incoming signal to a local common clock. In order to resolve the above described metastability problem, synchronizers of the prior art typically require a plurality of complete clock cycles to process an incoming signal. This leads to delays and is thus not desirable.
What is desired is a synchronizer arranged to rapidly detect a change in state in an incoming asynchronous signal so as to resolve any metastability with minimal latency.